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PLS159 Fiches technique(PDF) 10 Page - NXP Semiconductors

No de pièce PLS159
Description  Programmable logic sequencer 16 횞 45 횞 12
PDF  12 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PLS159 Fiches technique(HTML) 10 Page - NXP Semiconductors

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Philips Semiconductors Programmable Logic Devices
Product specification
PLS159A
Programmable logic sequencer
(16
× 45 × 12)
October 22, 1993
34
“OR” ARRAY – (Qn = J-K Type)
Q
J
K
Tn
M = DISABLED
ACTION
HOLD
CODE
Q
J
K
Tn
M = DISABLED
ACTION
RESET
CODE
L
Q
J
K
Tn
M = DISABLED
ACTION
SET
CODE
Q
J
K
Tn
ACTION
TOGGLE
CODE
O
–
H
M = DISABLED
“OR” ARRAY – (S or B)
“EX-OR” ARRAY – (B)
Tn STATUS
INACTIVE
CODE
•
Tn STATUS
ACTIVE1
CODE
A
Tn
S, B
Tn
POLARITY
LOW1
CODE
L
POLARITY
HIGH
CODE
H
S
B
S
B
S, B
“OE” ARRAY – (E)
ACTION
DISABLE
CODE
ACTION
ENABLE4
CODE
ACTION
CONTROL
CODE
ACTION
IDLE1, 4
CODE
O
–
A
En
OE
En
OE
En
OE
En
OE
•
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, FC, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, FC.
4. En = O and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of “OR” array links.



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