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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 65

9.1.9

Companding Threshold 2 Register (Address 0x08)

Figure 99:

CT2Reg

Address: 0x08

Default Value: 0x80

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Companding

Threshold 2

10000000b

It defines, in companding mode, the second

ADC step.

9.1.10

Companding Threshold 3 Register (Address 0x09)

Figure 100:

CT3Reg

Address: 0x09

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Companding

Threshold 3

00000000b

It defines, in companding mode, the third

ADC step.

9.1.11

End of Range Register (Address 0x0A)

Figure 101:

EORReg

Address: 0x0A

Default Value: 0xFF

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

End of Range Level

11111111b

It defines the digital level for the ADC

conversion.

This register sets the value for the end of range for the ADC, or the highest value the ADC will

compute. It is with this value that the conversion time for the ADC is defined. Since the ADC is 12-bit

and the register only holds 8-bit, the register holds the 8 MSB from a 12-bit word.

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