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TSL25721 Fiches technique(PDF) 26 Page - OSRAM GmbH |
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TSL25721 Fiches technique(HTML) 26 Page - OSRAM GmbH |
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26 / 41 page ![]() Datasheet, Public Page 25 [v2-00] 2022-Nov-30 Document Feedback TSL2572 − Register Overview Configuration Register (0x0D) The configuration register sets the wait long time and ALS gain level. Figure 28: Configuration Register Field Bits Description Reserved 7:3 Reserved. Write as 0. AGL 2 ALS gain level. When asserted, the 1x and 8x ALS gain (AGAIN) modes are scaled by 0.16. Otherwise, AGAIN is scaled by 1. Do not use with AGAIN greater than 8x. WLONG 1 Wait Long. When asserted, the wait cycles are increased by a factor 12x from that programmed in the WTIME register. Reserved 0 Reserved. Write as 0. 6 75 4 2 31 0 CONFIG Reserved WLONG Reset 0x00 AGL Reserved |
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