PCK2002MPW datasheet(5/12 Pages) PHILIPS

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Philips Semiconductors

Product data

PCK2002M

0–300 MHz I2C 1:10 clock buffer

2001 Jul 19

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

Tamb = 0°C to +70°C

UNIT

NOTES

MIN

TYP7

MAX

TSDRISE

SDRAM rise time

2, 4

1.5

2.0

4.0

V/ns

TSDFALL

SDRAM fall time

2, 4

1.5

2.9

4.0

V/ns

TPLH

SDRAM buffer LH propagation delay

4, 5

1.2

2.7

3.5

TPHL

SDRAM buffer HL propagation delay

4, 5

1.2

2.7

3.5

TPZL, TPZH

SDRAM buffer enable time

4, 5

1.0

2.6

5.0

TPLZ, TPHZ

SDRAM buffer disable time

4, 5

1.0

2.7

5.0

DUTY CYCLE

Output Duty Cycle

Measured at 1.5 V

3, 4, 5

TSDSKW

SDRAM Bus CLK skew

1, 4

—

150

250

TDDSKW

Device to device skew

—

500

NOTES:

1. Skew is measured on the rising edge at 1.5 V.

2. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.

3. Duty cycle should be tested with a 50/50% input.

4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5. Input edge rate for these tests must be faster than 1 V/ns.

6. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to

ensure duty cycle specification is met.

7. All typical values are at VCC = 3.3 V and Tamb = 25 °C.

8. Typical is measured with MAX (30 pF) discrete load.

9. Typical is measured with MIN (20 pF) discrete load.

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