Data Sheet

ADMV8505

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 31

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 5 to 27, 29, 31,

37, 39

GND

Ground. Connect the GND pins to the RF and DC ground.

2

VSS

The –2.5 V Power Supply Pin. Place 0.1 μF and 100 pF decoupling capacitors close to VSS.

4

RF1

RF Pin 1. RF1 is DC-coupled and matched to 50 Ω. Do not apply an external voltage to RF1.

28

RF2

RF Pin 2. RF2 is DC-coupled and matched to 50 Ω. Do not apply an external voltage to RF2.

30

VDD

The 3.3 V Power Supply Pin. Place 0.1 μF and 100 pF decoupling capacitors close to VDD.

32

BYP

The 2.5 V LDO Decoupling Bypass Pin. Place 47 μF, 0.1 μF, and 100 pF decoupling capacitors close to BYP.

33

SFL

SPI Fast Latch Enable, 3.3 V Logic. Set SFL high to enable fast latching of filter states on each rising edge of CS. While SFL is in

this mode, the SCLK, SDO, and SDI pins are not active. The SFL pin is internally pulled low with a 260 kΩ resistor.

34

SCLK

SPI Clock, 3.3 V Logic. The SCLK pin is internally pulled low with a 260 kΩ resistor.

35

SDO

SPI Data Output, 3.3 V Logic. The SDO pin is internally pulled low with a 260 kΩ resistor.

36

SDI

SPI Data Input, 3.3 V Logic. The SDI pin is internally pulled low with a 260 kΩ resistor.

38

CS

SPI Chip Select, 3.3 V Logic. Active low. The CS pin is internally pulled low with a 260 kΩ resistor.

40

RST

Chip Reset, 3.3 V Logic. Active low. The RST pin is internally pulled high with a 260 kΩ resistor

E1 to E16

EPAD

Exposed Pad. The exposed pad must be connected to the RF and DC ground.