AM29F400B_06 datasheet(17/43 Pages) AMD

17 / 43 page

November 1, 2006 21505E5

Am29F400B

D A TA

SH EE T

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the

operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. (Refer to “The Erase Resume command is

valid only during the Erase Suspend mode.” for infor-

mation on these status bits.)

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the “Erase/Program Operations” tables in

the “AC Characteristics” section for parameters, and to

Figure 14 for timing diagrams.

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