D1028AN9CPGRK-U datasheet(1/41 Pages) KINGSTON

No de pièce	D1028AN9CPGRK-U

Description	8G bits DDR4 SDRAM

PDF	41 Pages

Scroll/Zoom	100%

Fabricant	KINGSTON [Kingston Technology Far East Co. Ltd]

Site Internet	https://www.kingston.com/

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. ................................................................................. Document No. 4809540F-01F

DATASHEET

8G bits DDR4 SDRAM

D1028AN9CPGRK-U

(1024M words x 8 bits)

D1028AN9CPGXN-U

(1024M words x 8 bits)

D1028AN9CPGXNI-U

(1024M words x 8 bits)

D5116AN9CXGRK-U

(512M words x 16 bits)

D5116AN9CXGXN-U

(512M words x 16 bits)

D5116AN9CXGXNI-U

(512M words x 16 bits)

•

Specifications

•Density: 8G bits

•Organization

-64M words x 8 bits x 16 banks

-64M words x 16 bits x 8 banks

•Package

-78-ball FBGA

-96-ball FBGA

- Lead-free

- Halogen-free

•Power supply (JEDEC standard 1.2V)

- VDD = 1.2V

 0.06V

- VPP = 2.5V +0.25V / -0.125V

•Data rate

- 3200/2666Mbps

•16 or 8 internal banks

- 16 banks (4 banks x 4 bank groups) for x8 product

- 8 banks (4 banks x 2 bank groups) for x16 product

•Interface: Pseudo Open Drain (POD)

•Burst Length (BL): 8 and 4 with Burst Chop (BC)

•CAS Latency (CL): 11, 13, 15, 17, 18, 19, 20, 22

(18 is only for Read DBI)

•CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16, 18

•Precharge: auto precharge option for each burst access

•Refresh: auto-refresh, self-refresh

•Refresh cycles

Average refresh period

7.8

s at 0C  TC-Commercial Temperature  +85C

7.8

s at -40C  TC-Industrial Temperature  +85C

3.9

s at +85C < TC  +95C

•Operating case temperature range

- 0

C to +95C (Commercial Temperature)

- -40

C to +95C (Industrial Temperature)

•

Features

• Double-data-rate architecture: two data transfers per clock cycle.

• The high-speed data transfer is realized by the 8 bits prefetch

pipelined architecture.

• Bi-directional differential data strobe (DQS and /DQS) is

transmitted/received with data for capturing data at the receiver.

• DQS is edge-aligned with data for READs; center- aligned with

data for WRITEs.

• Differential clock inputs (CK_t and CK_c).

• DLL aligns DQ and DQS transitions with CK transitions.

• Data mask (DM) write data-in at the both rising and falling edges of

the data strobe.

• Write Cycle Redundancy Code (CRC) is supported.

• Programmable preamble for read and write is supported.

• Programmable burst length 4/8 with both nibble sequential and

interleave mode.

• BL switch on the fly.

• Driver strength selected by MRS.

• Dynamic On Die Termination supported.

• Two Termination States such as RTT_PARK and RTT_NOM

switchable by ODT pin.

• Asynchronous RESET pin supported.

• ZQ calibration supported.

• Write Levelization supported.

• This product in compliance with the RoHS directive.

• Internal Vref DQ level generation is available.

• TCAR(Temperature Controlled Auto Refresh) mode is supported.

• LP ASR(Low Power Auto Self Refresh) mode is supported.

• Command Address (CA) Parity (command/address) mode is

supported.

• Per DRAM Addressability (PDA).

• Fine granularity refresh is supported.

• Geardown Mode(1/2 rate, 1/4 rate) is supported.

• Self Refresh Abort is supported.

• Maximum power saving mode is supported.

• Banks Grouping is applied, and CAS to CAS latency(tCCD_L,

tCCD_S) for the banks in the same or different bank group accesses

are available.

• DMI pin support for write data masking and DBIdc functionality.

1

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