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PISOTMP35BDFQR Fiches technique(PDF) 21 Page - Texas Instruments |
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PISOTMP35BDFQR Fiches technique(HTML) 21 Page - Texas Instruments |
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21 / 28 page ![]() www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 2X .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25] .016-.050 [0.41-1.27] 4X (0 -15 ) 3X .050 [1.27] .081-.089 [2.07-2.27] 6X .012-.020 [0.31-0.50] .075 [1.91] A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max height DFQ0007A SMALL OUTLINE INTEGRATED CIRCUIT 4229018/A 10/2022 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. No JEDEC Registration as of September 2022 1 7 .010 [0.25] C A B 5 4 PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 www.ti.com ISOTMP35 SNIS232 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ISOTMP35 |
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