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DSP56F803 Fiches technique(PDF) 45 Page - Freescale Semiconductor, Inc |
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DSP56F803 Fiches technique(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 57 page ![]() 56F803 Technical Data, Rev. 16 40 Freescale Semiconductor Figure 3-21 SPI Slave Timing (CPHA = 1) 3.9 Quad Timer Timing Table 3-13 Timer Timing1, 2 Operating Conditions: V SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Min Max Unit Timer input period PIN 4T+6 — ns Timer input high/low period PINHL 2T+3 — ns Timer output period POUT 2T — ns SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 MSB in Bits 14–1 LSB in SS (Input) Slave LSB out tC tCL tDV tA tELD tR tF tELG tCH tCL tCH tF tDS tDV tDI tDH tD tR |
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