56F803 datasheet(13/57 Pages) FREESCALE

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56F803 Technical Data, Rev. 16

Freescale Semiconductor

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2-1

and as illustrated in Figure 2-1. In Table 2-2 through Table 2-17, each table row describes the signal or

signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of

Pins

Detailed

Description

Power (VDD or VDDA)7

Table 2-2

Ground (VSS or VSSA)7

Table 2-3

Supply Capacitors

Table 2-4

PLL and Clock

Table 2-5

Address Bus1

Table 2-6

Data Bus

Table 2-7

Bus Control

Table 2-8

Interrupt and Program Control

Table 2-9

Pulse Width Modulator (PWM) Port

Table 2-10

Serial Peripheral Interface (SPI) Port1

Alternately, GPIO pins

Table 2-11

Quadrature Decoder Port2

Alternately, Quad Timer pins

Table 2-12

Serial Communications Interface (SCI) Port1

Table 2-13

CAN Port

Table 2-14

Analog to Digital Converter (ADC) Port

Table 2-15

Quad Timer Module Port

Table 2-16

JTAG/On-Chip Emulation (OnCE)

Table 2-17

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