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AT80C51RB2-3CSIM Fiches technique(PDF) 37 Page - ATMEL Corporation |
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AT80C51RB2-3CSIM Fiches technique(HTML) 37 Page - ATMEL Corporation |
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37 / 83 page ![]() 38 AT80C51RD2/AT83C51Rx2 4113B–8051–03/05 Table 20. SADDR Register SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 17. Baud Rate selection Table 21. Baud Rate Selection Table UART 765 43210 TCLK (T2CON) RCLK (T2CON) TBCK (BDRCON) RBCK (BDRCON) Clock Source UART Tx Clock Source UART Rx 00 00 Timer 1 Timer 1 10 00 Timer 2 Timer 1 01 00 Timer 1 Timer 2 11 00 Timer 2 Timer 2 X 0 1 0 INT_BRG Timer 1 X 1 1 0 INT_BRG Timer 2 0 X 0 1 Timer 1 INT_BRG 1 X 0 1 Timer 2 INT_BRG X X 1 1 INT_BRG INT_BRG RCLK / 16 RB CK INT_BRG 0 1 TIMER1 0 1 0 1 TIMER2 INT_B RG TIMER1 TI ME R2 TI ME R_BRG_RX Rx Clock / 16 0 1 TIMER_BRG_TX Tx Clock TB CK TCLK |
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