AT43USB326 datasheet(25/102 Pages) ATMEL

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AT43USB326

3313D–USB–04/06

Timer/Counter Interrupt Mask Register – TIMSK

• Bit 7:2 – Res: Reserved Bits

These bits are reserved bits in the AT43USB326 and always read zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is

executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB326 and always reads zero.

Timer/Counter Interrupt Flag Register – TIFR

• Bit 7:2 – Res: Reserved Bits

These bits are reserved bits in the AT43USB326 and always read zero.

• Bit 1 – TOV: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the

hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is

cleared by writing a logic one to the flag. When the SREG I- bit, and TOIE0 (Timer/Counter0

Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is

executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB326 and always reads zero.

Bit

210

$39 ($59)

––

–

TOIE0

–

TIMSK

Read/Write

R/W

Initial Value

Bit

210

$38 ($58)

––

–

TOV0

–

TIFR

Read/Write

R/W

Initial Value

AT43USB326 Fiches technique(PDF) 25 Page - ATMEL Corporation

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