WM8738

Production Data

w

PD Rev 4.4 August 2006

9

INTERNAL POWER ON RESET CIRCUIT

Power On Reset

Circuit

AVDD

100K

100K

CAP

DVDD

INTERNAL PORB

VDD

T1

T2

Figure 2 Internal Power On Reset Circuit Schematic

The WM8738 includes an internal Power On Reset Circuit which is used reset the digital logic into a

default state after power up.

Figure 2 shows a schematic of the internal POR circuit. The circuit monitors DVDD and CAP and

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until

AVDD and DVDD and CAP are established. When AVDD, DVDD, and CAP have been established,

PORB is released high, all registers are in their default state and writes to the digital interface may

take place.

On power down, PORB is asserted low whenever DVDD or CAP drop below the minimum threshold

In most applications the time required for the device to release PORB high will be determined by the

charge time of the CAP node.