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CAT1232LPWT2 Fiches technique(PDF) 8 Page - Catalyst Semiconductor |
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CAT1232LPWT2 Fiches technique(HTML) 8 Page - Catalyst Semiconductor |
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8 / 12 page ![]() 8 CAT1232LP/CAT1832 Doc. No. 25089, Rev. 0C © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice PACKAGE DRAWING 8-LEAD DIP (300mil) Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 A e b E1 b2 L A2 A1 E D eB 24C16_8-LEAD_DIP_(300P).eps SYMBOL A A1 b b2 D E E1 e eB L MIN 0.38 0.36 9.02 7.62 6.17 6.35 7.87 2.79 3.81 NOM 0.46 1.52 1.14 7.87 2.54 BSC MAX 4.57 A2 3.05 3.81 0.56 10.16 8.26 7.49 9.65 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. |
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