CAT25C17API-20T datasheet(6/10 Pages) CATALYST

No de pièce	CAT25C17API-20T

Description	16K-Bit CMOS PARALLEL EEPROM

PDF	10 Pages

Scroll/Zoom	100%

Fabricant	CATALYST [Catalyst Semiconductor]

Site Internet	http://www.catalyst-semiconductor.com

Logo

6 / 10 page

CAT28C17A

Doc. No. 1075, Rev. B

ADDRESS

tRC

DATA OUT

DATA VALID

tCE

tOE

tOH

tAA

tOHZ

tHZ

VIH

HIGH-Z

tLZ

tOLZ

DEVICE OPERATION

Read

Data stored in the CAT28C17A is transferred to the data

bus when WE is held high, and both OE and CE are held

low. The data bus is set to a high impedance state when

either CE or OE goes high. This 2-line control architec-

ture can be used to eliminate bus contention in a system

environment.

Figure 4. Byte Write Cycle [WE Controlled]

ADDRESS

tAS

DATA IN

DATA VALID

tCS

tAH

tCH

tWC

tOEH

tDL

tDH

tDS

tOES

tWP

RDY/BUSY

tDB

DATA OUT

HIGH-Z

Ready/BUSY (RDY/BUSY)

The RDY/BUSY pin is an open drain output which

indicates device status during programming. It is pulled

low during the write cycle and released at the end of

programming. Several devices may be OR-tied to the

same RDY/BUSY line.

Figure 3. Read Cycle

CAT25C17API-20T Fiches technique(PDF) 6 Page - Catalyst Semiconductor

CAT25C17API-20T Fiches technique(HTML) 6 Page - Catalyst Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10

Fiches technique Télécharger

Lien URL