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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ES9028Q2M Fiches technique(PDF) 28 Page - ESS Technology,Inc |
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ES9028Q2M Fiches technique(HTML) 28 Page - ESS Technology,Inc |
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28 / 45 page  0.41 January 16, 2020 ES9028Q2M Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643- 8800 • WWW.ESSTECH.COM 28 Register #69-66: DPLL Ratio 32 bit, Read-Only Register. Register #69 contains the MSBs, Register #66 contains the LSBs Bits [31:0] Mnemonic dpll_num This is a read-only 32bit value that can be used to calculate the sample rate. The raw sample rate (FSR) can be calculated using: FSR = (DPLL_NUM x FMCLK) / 232. Note that the DPLL number (register 66-69) should be read from LSB to MSB as it is latched on the LSBs (register 66). Register #74-70: Channel Status Register #74 contains the MSBs, Register #70 contains the LSBs Format is [191:0] These registers allow read back of the SPDIF channel status. The status definition is different for the consumer configuration and professional configuration. Please refer to the following two tables for details. |
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