STE100A datasheet(1/82 Pages) STMICROELECTRONICS

No de pièce	STE100A

Description	PCI 10/100 Ethernet controller with integrated PHY (3.3V)

PDF	82 Pages

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Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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1 / 82 page

February 2007

Rev 8

1/82

82

STE10/100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Features

■ IEEE802.3u 100BASE-TX and IEEE802.3

10BASE-T compliant

■ Support for IEEE802.3x flow control

■ IEEE802.3u auto-negotiation support for

10BASE-T and 100BASE-TX

■ PCI bus interface rev. 2.2 compliant

■ ACPI and PCI power management standard

compliant

■ Support for PC99 wake on LAN

■ Provides 32-bit PCI bus master data transfer at

PCI clocks of 20-33 MHz

■ Provides writable EEPROM/Boot rom interface

■ Provides independent transmission and

receiving FIFOs, each 2k bytes long

■ Supports big endian or little endian byte

ordering

■ ACPI and PCI compliant power management

functions offer significant power-savings

performance

■ Provides general purpose timers

■ 128-pin QFP package

Description

The STE10/100A is a high performing PCI fast

ethernet controller with integrated physical layer

interface for 10BASE-T and 100BASE-TX

applications.

It was designed with advanced CMOS technology

to provide glueless 32-bit bus master interface for

PCI bus, boot ROM interface, CSMA/CD protocol

for fast ethernet, as well as the physical media

interface for 100BASE-TX of IEEE802.3u and

10BASE-T of IEEE802.3. The auto-negotiation

function is also supported for speed and duplex

detection.

The STE10/100A provides both half-duplex and

full-duplex operation, as well as support for full-

duplex flow control. It provides long FIFO buffers

for transmission and receiving, and early interrupt

mechanism to enhance performance. The

STE10/100A also supports ACPI and PCI

compliant power management function

PQFP128 (14mm x 20mm x 2.7mm)

www.st.com

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