CSB1000JA datasheet(46/153 Pages) STMICROELECTRONICS

46 / 153 page

ST72334J/N, ST72314J/N, ST72124J

46/153

13 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over

several different features such as the external in-

terrupts or the I/O alternate functions.

13.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by

the ISxx bits of the MISCR1 miscellaneous regis-

ter. This control allows to have two fully independ-

ent external interrupt source sensitivities.

Each external interrupt source can be generated

on four different events on the pin:

Falling edge

Rising edge

Falling and rising edge

Falling edge and low level

To guarantee correct functionality, the sensitivity

bits in the MISCR1 register must be modified only

when the I bit of the CC register is set to 1 (inter-

rupt masked). See I/O port register and Miscella-

neous register descriptions for more details on the

programming.

13.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers manage four I/O port miscel-

laneous alternate functions:

Main clock signal (fCPU) output on PF0

A beep signal output on PF1 (with 3 selectable

audio frequencies)

SPI pin configuration:

–SS pin internal control to use the PC7 I/O port

function while the SPI is active.

These functions are described in detail in the Sec-

tion 13 "MISCELLANEOUS REGISTERS" on

page 46.

Figure 28. Ext. Interrupt Sensitivity

ei2

INTERRUPT

SOURCE

IS10

IS11

MISCR1

SENSITIVITY

CONTROL

PB1

PB2

PB0

PB3

PB5

PB6

PB4

PB7

ei3

ei0

INTERRUPT

SOURCE

IS20

IS21

MISCR1

SENSITIVITY

CONTROL

PA1

PA2

PA0

PA3

PF1

PF2

PF0

ei1

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