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PIC12F683 Fiches technique(PDF) 39 Page - Microchip Technology |
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PIC12F683 Fiches technique(HTML) 39 Page - Microchip Technology |
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39 / 148 page ![]() 2004 Microchip Technology Inc. Preliminary DS41211B-page 37 PIC12F683 4.2.4.6 GP5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: • a general purpose I/O •a TMR1 clock input • a crystal/resonator connection • a clock input FIGURE 4-6: BLOCK DIAGRAM OF GP5 I/O pin VDD VSS D Q CK Q D Q CK Q D Q CK Q D Q CK Q VDD D EN Q D EN Q Weak Data WR WPU RD WPU RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC To TMR1 or CLKGEN INTOSC Mode RD GPIO INTOSC Mode GPPU OSC2 (1) Note 1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. TMR1LPEN(1) Interrupt-on- change Oscillator Circuit Bus Q3 |
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