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L6730CQ Fiches technique(PDF) 41 Page - STMicroelectronics |
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L6730CQ Fiches technique(HTML) 41 Page - STMicroelectronics |
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41 / 50 page ![]() L6730C - L6730D I/O Description 41/50 SYNCH This pin is connected to the synch pin of the controller (see Chapter 5.11 on page 26). PWRGD This pin is connected to the PGOOD pin of the controller. DIP SWITCH Different positions of the dip switch correspond to different settings of the multifunction pin (S/O/U) (CC/O/U). Table 11. Dip switch UVLO OVP SINK CC Vsou/VCCDR DIP SWITCH STATE 5V Not Latched Not 0 S7 A 5V Not Latched Yes 0.2 S1-S7 B 5V Latched Not 0.3 S2-S7 C 5V Latched Yes 0.4 S3-S7 D 12V Not Latched Not 0.5 S4-S7 E 12V Not Latched Yes 0.6 S5-S7 F 12V Latched Not 0.7 S6-S7 G 12V Latched Yes 1 S1 H Table 10. I/O Functions |
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