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L6726ATR Fiches technique(PDF) 16 Page - STMicroelectronics |
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L6726ATR Fiches technique(HTML) 16 Page - STMicroelectronics |
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16 / 24 page ![]() Application details L6726A 16/24 depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage ∆VOSC. VOUT is scaled and transferred to FB node by the output resistor divider. The compensation network closes the loop joining FB and COMP node with transfer function ideally equal to -gm ·Z F. Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved giving an integrator shape to compensation network transfer function. Loop bandwidth (F0dB) can be fixed choosing the right RF; however, for stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain has to cross 0dB axis with -20dB/decade slope. As an example, Figure 9 shows an asymptotic bode plot of a type II compensation. Figure 9. Example of type II compensation. ● Open loop converter singularities: a) b) ● Compensation Network singularities frequencies: a) b) Gain [dB] Log (Freq) 0dB OTA open loop gain closed loop gain compensation gain converter open loop gain F LC F ESR F Z F P 20log (gm·R F) 20log [V IN/∆VOSC·ROS/(RFB+ROS)] F 0dB F LC 1 2 π LC OUT ⋅ ------------------------------------- = F ESR 1 2 π C OUT ESR ⋅⋅ ------------------------------------------------- = F Z 1 2 π R F C F ⋅⋅ ------------------------------------ = F P 1 2 π R F C F C P ⋅ C F C P + ---------------------- ⎝⎠ ⎛⎞ ⋅⋅ -------------------------------------------------------- = |
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