Nexperia

74AHCT240

Octal buffer/line driver; inverting; 3-state

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 9.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig. 7. Test circuit for measuring switching times

Table 9. Test data

Input

Load

S1 position

VI

tr, tf

CL

RL

tPHL, tPLH

tPZH, tPHZ

tPZL, tPLZ

3.0 V

3.0 ns

15 pF, 50 pF

1 kΩ

open

GND

VCC

74AHCT240

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© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 6 — 29 June 2020

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