Nexperia

74ALVT162821

20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state

10.1. Waveforms and test circuit

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nCP input

nQn output

tPHL

tPLH

tW

VOH

VI

GND

VOL

VM

VM

VM

1/fmax

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 6. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock

frequency

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GND

GND

th

tsu

th

tsu

VM

VM

VM

VI

VOH

VOL

VI

nQn output

nCP input

nDn input

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 7. Set-up times and hold times from input (nDn) to clock (nCP)

74ALVT162821

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Product data sheet

Rev. 5 — 19 October 2020

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