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LTC2440IGN Fiches technique(PDF) 4 Page - Linear Technology

No de pièce LTC2440IGN
Description  24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution
PDF  28 Pages
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Fabricant  LINER [Linear Technology]
Site Internet  http://www.linear.com
Logo LINER - Linear Technology

LTC2440IGN Fiches technique(HTML) 4 Page - Linear Technology

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LTC2440
4
sn2440, 2440fas
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage
●
4.5
5.5
V
ICC
Supply Current
Conversion Mode
CS = 0V (Note 7)
●
811
mA
Sleep Mode
CS = VCC (Note 7)
●
830
µA
The
● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
POWER REQUIRE E TS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
●
0.1
20
MHz
tHEO
External Oscillator High Period
●
25
10000
ns
tLEO
External Oscillator Low Period
●
25
10000
ns
tCONV
Conversion Time
OSR = 256 (SDI = 0)
●
0.99
1.13
1.33
ms
OSR = 32768 (SDI = 1)
●
126
145
170
ms
External Oscillator (Note 10, 13)
●
40 • OSR + 170
fEOSC(kHz)
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
●
0.8
0.9
1
MHz
External Oscillator (Notes 9, 10)
fEOSC/10
Hz
DISCK
Internal SCK Duty Cycle
(Note 9)
●
45
55
%
fESCK
External SCK Frequency Range
(Note 8)
●
20
MHz
tLESCK
External SCK Low Period
(Note 8)
●
25
ns
tHESCK
External SCK High Period
(Note 8)
●
25
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
●
41.6
35.3
30.9
µs
External Oscillator (Notes 9, 10)
●
320/fEOSC
s
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 8)
●
32/fESCK
s
t1
CS
↓ to SDO Low Z
(Note 12)
●
025
ns
t2
CS
↑ to SDO High Z
(Note 12)
●
025
ns
t3
CS
↓ to SCK ↓
(Note 9)
5
µs
t4
CS
↓ to SCK ↑
(Notes 8, 12)
●
25
ns
tKQMAX
SCK
↓ to SDO Valid
●
25
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
●
15
ns
t5
SCK Set-Up Before CS
↓
●
50
ns
t7
SDI Setup Before SCK
↑
●
10
Note 5
ns
t8
SDI Hold After SCK
↑
●
10
Note 5
ns
The
● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
TI I G CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5 to 5.5V unless otherwise specified.
VREF = REF
+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator. FO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1
µs (typical) to
the conversion time.



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