Nexperia

74LVC2G126

Dual bus buffer/line driver; 3-state

VEXT

VCC

VI

VO

mna616

DUT

CL

RT

RL

RL

G

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig. 7. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

Input

Load

VEXT

VCC

VI

tr, tf

CL

RL

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 kΩ

open

GND

2 × VCC

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500 Ω

open

GND

2 × VCC

2.7 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

GND

6 V

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

GND

6 V

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500 Ω

open

GND

2 × VCC

74LVC2G126

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 15 — 28 April 2020

8 / 17