CDP1802AC/3

FN1441 Rev 3.00

Page 6 of 27

October 17, 2008

Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 VDD Point. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

PARAMETERS

VDD (V)

-55°C TO +25°C

+125°C

UNITS

MIN

MAX

MIN

MAX

PROGAGATION DELAY TIMES, tPLH, tPHL

Clock to TPA, TPB

5

-

275

-

370

ns

Clock-to-Memory High Address Byte, tPLH, tPHL

5

-

725

-

950

ns

Clock-to-Memory Low Address Byte Valid, tPLH, tPHL

5

-

340

-

425

ns

Clock to MRD, tPLH, tPHL

5

-

340

-

425

ns

Clock to MWR, tPLH, tPHL

5

-

275

-

370

ns

Clock to (CPU DATA to BUS) Valid, tPLH, tPHL

5

-

430

-

550

ns

Clock to State Code, tPLH, tPHL

5

-

440

-

550

ns

Clock to Q, tPLH, tPHL

5

-

375

-

475

ns

Clock to N (0 to 2), tPLH, tPHL

5

-

400

-

525

ns

INTERFACE TIMING REQUIREMENTS (Note 7)

Data Bus Input Setup, tSU

510

-

10

-

ns

Data Bus Input Hold, tH

5

175

-

230

-

ns

DMA Setup, tSU

510

-

10

-

ns

DMA Hold, tH

5

200

-

270

-

ns

Interrupt Setup, tSU

510

-

10

-

ns

Interrupt Hold, tH

5

175

-

230

-

ns

WAIT Setup, tSU

530

-

30

-

ns

EF1-4 Setup, tSU

520

-

20

-

ns

EF1-4 Hold, tH

5

100

-

135

-

ns

REQUIRED PULSE WIDTH TIMES

CLEAR Pulse Width, tWL

5

150

-

200

-

ns

CLOCK Pulse Width, tWL

5

140

-

185

-

ns

NOTE:

7. Minimum input setup and hold times required by Part CDP1802AC/3.