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ICS954321 Fiches technique(PDF) 7 Page - Renesas Technology Corp

No de pièce ICS954321
Description  Programmable Timing Control Hub™ for P4™ processor
PDF  19 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS954321 Fiches technique(HTML) 7 Page - Renesas Technology Corp

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7
Integrated
Circuit
Systems, Inc.
ICS954321
1078B—09/20/05
SMBus Table: Output Control Register
Control
Function
Bit 7
CPUCLK2_ITP/SRCCLK10
Enable
Output Enable
RW
1
Bit 6
SRCCLK7 Enable
Output Enable
RW
1
Bit 5
SRCCLK5 Enable
Output Enable
RW
1
Bit 4
SRCCLK4 Enable
Output Enable
RW
1
Bit 3
SRCCLK3 Enable
Output Enable
RW
1
Bit 2
SRCCLK2 Enable
Output Enable
RW
1
Bit 1
SRCCLK1 Enable
Output Enable
RW
1
Bit 0
LCDCLK/SRCCLK0 Enable
Output Enable
RW
1
SMBus Table: Spread and Output Control Register
Control
Function
Bit 7
Test Clock Mode Entry
Test Mode
RW
0
Bit 6
DOT_96MHz Enable
Output Enable
RW
1
Bit 5
USB_48MHz Enable
Output Enable
RW
1
Bit 4
REFOUT Enable
Output Enable
RW
1
Bit 3
LCDCLK Spectrum Mode
Spread Control
RW
1
Bit 2
CPUCLK1
Output Enable
RW
1
Bit 1
CPUCLK0
Output Enable
RW
1
Bit 0
Spread Spectrum Mode
Spread Control for PLL1
RW
0
SMBus Table: Output Control Register
Control
Function
Bit 7
PCICLK3
Output Enable
RW
1
Bit 6
PCICLK2
Output Enable
RW
1
Bit 5
PCICLK1
Output Enable
RW
1
Bit 4
PCICLK0
Output Enable
RW
1
Bit 3
Test Mode Selection
Test Mode Selection
RW
0
Bit 2
PCI_STOP
Stop all PCI clocks
RW
1
Bit 1
PCI_F0 Enable
Output Enable
RW
1
Bit 0
1
SMBus Table: Output Control Register
Control
Function
Bit 7
-
Bit 6
SRCCLK9 Enable
Output Enable
RW
1
Bit 5
SRCCLK8 Enable
Output Enable
RW
1
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
SMBus Table:Output Control Register
Control
Function
Bit 7
1
Bit 6
96MHz
Driven in PD
RW
1
Bit 5
REFOUT STRENGTH
Strength Programming
RW
1
Bit 4
1
Bit 3
PCI_F0
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCICLK_F output.
RW
1
Bit 2
CPUCLK2_ITP
RW
1
Bit 1
CPUCLK1
RW
1
Bit 0
CPUCLK0
RW
1
Disable
4
3
-
6
-
64
-
-
0
Byte 3
Hi-Z
Pin #
Name
Type
Disable
Reserved
0
Disable
Byte 2
Pin #
Name
Type
5
PWD
PWD
Enable
1
Enable
Disable
Enable
1
REF/N
Enable
-
-
Enable
PWD
Disable
Disable
38, 37
41, 40
Enable
Enable
Type
Free Running
0
1X
Hi-Z
2X
Free Running
Free Running
Stoppable
Name
-
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
-
-
-
1
Stoppable
Stoppable
Stoppable
Reserved
Driven
Free Running
Reserved
-
-
Pin #
-
Byte 4
-
-
-
PWD
36, 35
Byte 0
Pin #
Name
Type
44, 43
Disable
Disable
Enable
01
Disable
Enable
20, 19
18, 17
31, 30
27, 26
25, 24
23, 22
PWD
01
Byte 1
Pin #
Name
Type
Disable
Enable
Enable
Enable
Disable
Disable
OFF
ON
52, 51
-
Enable
Disable
Enable
60
-
-
49, 48
12
Enable
Disable
Enable
Disable
15, 14
Disable
Enable
Disable
Enable
Disable
Enable
OFF
ON
Disable
Enable
Disable
Enable
Reserved
Reserved
Reserved
Reserved
Enable
Disable
Disable
Reserved
Reserved



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