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ICS952702 Fiches technique(PDF) 10 Page - Renesas Technology Corp

No de pièce ICS952702
Description  Programmable Timing Control Hub for K7TM System
PDF  18 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS952702 Fiches technique(HTML) 10 Page - Renesas Technology Corp

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10
Integrated
Circuit
Systems, Inc.
ICS952702
0795D—05/06/05
Absolute Maximum Ratings
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2
VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
5mA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
mA
Operating Supply
Current
IDD(op)
Full Active, CL = full load; Select @ 100MHz
180
250
mA
Power Down Supply
Current
IDDPD
All diff pairs tri-stated
1.2
12
mA
Input frequency
Fi
VDD = 3.3 V;
11
14.318
16
MHz
CIN
Logic Inputs
5
pF
CINX
X1 & X2 pins
27
30
45
pF
Spread Modulation
Frequency
1
fSS
320
33
KHz
Clk Stabilization
1
TSTAB
From VDD Power-Up of de-assertion of PD#
to 1st clock.
1.8
ms
Skew
TCPU-AGP
CPU @ crossing, AGP @ 1.5V
2.5
3.1
3.5
ns
Skew
TCPU-ZCLK
CPU @ crossing, ZCLK @ 1.5V
2.5
3.3
3.5
ns
Skew
1
TCPU-PCI
VT = 1.5 V CPU @ crossing, PCI @ 1.5V
2.5
2.9
3.5
ns
1Guaranteed by design, not 100% tested in production.
Input Capacitance
1



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