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AM29BDS643G Fiches technique(PDF) 38 Page - SPANSION |
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AM29BDS643G Fiches technique(HTML) 38 Page - SPANSION |
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38 / 49 page ![]() 36 Am29BDS643G 25692A2 May 8, 2006 D A TA SH EE T AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter Description All Speed Options Unit JEDEC Std tReadyw RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 μs RESET# tRP tReady Reset Timings NOT during Embedded Algorithms tReadyw CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP Figure 12. Reset Timings |
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