 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
ICS1893CF Fiches technique(PDF) 72 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
ICS1893CF Fiches technique(HTML) 72 Page - Renesas Technology Corp |
|
|
72 / 127 page  ICS1893CF, Rev. K, 05/13/10 May, 2010 72 Chapter 7 Management Register Set ICS1893CF Data Sheet - Release Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. 7.12 Register 17: Quick Poll Detailed Status Register Table 7-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of the ICS1893CF operations. During reset, it is initialized to pre-defined default values. Note: 1. For an explanation of acronyms used in Table 7-18, see Chapter 1, “Abbreviations and Acronyms”. 2. Most of this register’s bits are latching high or latching low, which allows the ICS1893CF to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.) 3. Although some of these status bits are redundant with other management registers, the ICS1893CF provides this group of bits to minimize the number of Serial Management Cycles required to collect the status data. Table 7-18. Quick Poll Detailed Status Register (register 17 [0x11]) Bit Definition When Bit = 0 When Bit = 1 Ac- cess SF De- fault Hex 17.15 Data rate 10 Mbps 100 Mbps RO – – – 17.14 Duplex Half duplex Full duplex RO – – 17.13 Auto-Negotiation Progress Monitor Bit 2 Reference Decode Table Reference Decode Table RO LMX 0 17.12 Auto-Negotiation Progress Monitor Bit 1 Reference Decode Table Reference Decode Table RO LMX 0 17.11 Auto-Negotiation Progress Monitor Bit 0 Reference Decode Table Reference Decode Table RO LMX 0 0 17.10 100Base-TX signal lost Valid signal Signal lost RO LH 0 17.9 100BasePLL Lock Error PLL locked PLL failed to lock RO LH 0 17.8 False Carrier detect Normal Carrier or Idle False Carrier RO LH 0 17.7 Invalid symbol detected Valid symbols observed Invalid symbol received RO LH 0 0 17.6 Halt Symbol detected No Halt Symbol received Halt Symbol received RO LH 0 17.5 Premature End detected Normal data stream Stream contained two IDLE symbols RO LH 0 17.4 Auto-Negotiation complete Auto-Negotiation in process Auto-Negotiation complete RO – 0 17.3 100Base-TX signal detect Signal present No signal present RO – 0 0 17.2 Jabber detect No jabber detected Jabber detected RO LH 0 17.1 Remote fault No remote fault detected Remote fault detected RO LH 0 17.0 Link Status Link is not valid Link is valid RO LL 0 |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
