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ADAV400 Fiches technique(PDF) 6 Page - Analog Devices

No de pièce ADAV400
Description  Audio Codec with Embedded SigmaDSP Processor
PDF  36 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADAV400 Fiches technique(HTML) 6 Page - Analog Devices

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ADAV400
Rev. 0 | Page 6 of 36
DIGITAL TIMING
Table 2.
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
fMCLKI (MCLKI Frequency)
3.024
24.576
MHz
tMCH (MCLKI High)
10
ns
tMCL (MCLKI Low)
10
ns
tRLPW (RESET Low Pulse Width)
20
ns
I2C PORT
fSCL (SCL Clock Frequency)
400
kHz
tSCLH (SCL High)
0.6
μs
tSCLL (SCL Low)
1.3
μs
Start Condition
tSCS (Setup Time)
0.6
μs
Relevant for repeated start condition
tSCH (Hold Time)
0.6
μs
The first clock is generated after this period
tDS (Data Setup Time)
100
ns
tSCR (SCL Rise Time)
300
ns
tSCF (SCL Fall Time)
300
ns
tSDR (SDA Rise Time)
300
ns
tSDF (SDA Fall Time)
300
ns
Stop Condition
tSCSH (Setup Time)
0.6
μs
SERIAL PORTS
Slave Mode
tSBH (BCLKx High)
40
ns
tSBL (BCLKx Low)
40
ns
fSBF (BCLKx Frequency)
64 × fS
tSLS (LRCLKx Setup)
10
ns
To BCLK rising edge
tSLH (LRCLKx Hold)
10
ns
From BCLK rising edge
tSDS (SDINx Setup)
10
ns
To BCLK rising edge
tSDH (SDINx Hold)
10
ns
From BCLK rising edge
tSDD (SDOx Delay)
40
ns
From BCLK falling edge
Master Mode
tMLD (LRCLKx Delay)
5
ns
From BCLK falling edge
tMDD (SDOx Delay)
40
ns
From BCLK falling edge
tMDS (SDINx Setup)
10
ns
From BCLK rising edge
tMDH (SDINx Hold)
10
ns
From BCLK rising edge



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