TL16C752BTPTREP datasheet(13/35 Pages) TI

13 / 35 page

TL16C752B-EP

3.3-V DUAL UART WITH 64-BYTE FIFO

SGLS153 – FEBRUARY 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

functional description (continued)

programmable baud rate generator

The TL16C752B-EP UART contains a programmable baud generator that takes any clock input and divides it

by a divisor in the range between 1 and (216–1). An additional divide-by-4 prescaler is also available and can

be selected by MCR[7], as shown in Figure 9. The output frequency of the baud rate generator is 16x the baud

rate. The formula for the divisor is:

divisor = (XTAL1 crystal input frequency/prescaler) / (desired baud rate

× 16)

where:

prescaler

1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)

4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected)

NOTE:

The default value of prescaler after reset is divide-by-1.

Figure 9 shows the internal prescaler and baud rate generator circuitry.

Prescaler Logic

(Divide By 1)

Prescaler Logic

(Divide By 4)

Internal

Oscillator

Logic

Baud Rate

Generator

Logic

XTAL1

XTAL2

Internal

Baud Rate

Clock

for Transmitter

and Receiver

MCR[7] = 0

MCR[7] = 1

Input Clock

Reference

Clock

Figure 9. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and

most significant byte of the baud rate divisor. If DLL and DLH value are both zero, the UART is effectively

disabled, as no baud clock is generated.

NOTE:

The programmable baud rate generator is provided to select both the transmit and receive clock

rates.

Table 5 and Table 6 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and

3.072 MHz respectively.

Figure 10 shows the crystal clock circuit reference.

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