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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ADF4002 Fiches technique(PDF) 4 Page - Analog Devices |
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ADF4002 Fiches technique(HTML) 4 Page - Analog Devices |
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4 / 24 page  ADF4002 Rev. 0 | Page 4 of 24 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.1 Table 2. Parameter Limit (B Version)2 Unit Test Conditions/Comments t1 10 ns min DATA to CLK setup time t2 10 ns min DATA to CLK hold time t3 25 ns min CLK high duration t4 25 ns min CLK low duration t5 10 ns min CLK to LE setup time t6 20 ns min LE pulse width 1 Guaranteed by design, but not production tested. 2 Operating temperature range (B version) is –40°C to +85°C. Timing Diagram CLK DB22 DB2 DATA LE t1 LE DB23 (MSB) t2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t3 t4 t6 t5 Figure 2. Timing Diagram |
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