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ICS853S024 Fiches technique(PDF) 10 Page - Renesas Technology Corp

No de pièce ICS853S024
Description  Low Skew, 1-to-24, Differential-to-3.3V, 2.5V LVPECL Fanout Buffer
PDF  20 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS853S024 Fiches technique(HTML) 10 Page - Renesas Technology Corp

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ICS853S024AY REVISION A JULY 20, 2011
10
©2011 Integrated Device Technology, Inc.
ICS853S024 Data Sheet
LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3E. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 3D. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
LVPECL
Input
CML
2.5V
Zo = 50
Ω
Zo = 50
Ω
2.5V
2.5V
R1
50
Ω
R2
50
Ω
R3
250
Ω
R4
250
Ω
R1
62.5
Ω
R2
62.5
Ω
2.5V
Zo = 50
Ω
Zo = 50
Ω
PCLK
nPCLK
2.5V
2.5V
LVPECL
LVPECL
Input
2.5V
R1
100
Ω
LVDS
PCLK
nPCLK
2.5V
LVPECL
Input
Zo = 50
Ω
Zo = 50
Ω
PCLK
nPCLK
2.5V
LVPECL
Input
2.5V
Zo = 50
Ω
Zo = 50
Ω
R1
100
Ω
CML Built-In Pullup
R6
100
Ω-180Ω
3.3V LVPECL Driv er
R7
100
Ω-180Ω
Zo = 50
Ω
R2
100
Ω
C1
Zo = 50
Ω
R3
100
Ω
C2
R4
100
Ω
R1
100
Ω
2.5V
3.3V
PCLK
nPCLK



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