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M95M02-DF Fiches technique(PDF) 13 Page - STMicroelectronics

No de pièce M95M02-DF
Description  2-Mbit serial SPI bus EEPROM
PDF  45 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95M02-DF Fiches technique(HTML) 13 Page - STMicroelectronics

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6.2
Write disable (WRDI)
One way of resetting the WEL bit is to send a write disable instruction to the device.
As shown in Figure 9, to send this instruction to the device, chip select (S) is driven low, and the bits of the
instruction byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high.
The write enable latch (WEL) bit, in fact, becomes reset by any of the following events:
•
Power-up
•
WRDI instruction execution
•
WRSR instruction completion
•
WRITE instruction completion.
Figure 9. Write disable (WRDI) sequence
C
D
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
S
M95M02-DR M95M02-DF
Write disable (WRDI)
DS7024 - Rev 13
page 13/45



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