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ILPS28QSWTR Fiches technique(PDF) 34 Page - STMicroelectronics |
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ILPS28QSWTR Fiches technique(HTML) 34 Page - STMicroelectronics |
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34 / 52 page ![]() When the ODR bits are set to 0000, the device is in power-down mode. When the device is in power-down mode, almost all internal blocks of the device are switched off to minimize power consumption. The digital interface is still active to allow communication with the device. The content of the configuration registers is preserved and output data registers are not updated, therefore keeping the last data sampled in memory before going into power-down mode. If the ONESHOT bit in CTRL_REG2 (11h) is set to 1, one-shot mode is triggered and a new acquisition starts when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR bits set to 0000). Once the acquisition is completed and the output registers updated, the device automatically enters in power-down mode. The ONESHOT bit self-clears itself. When the ODR bits are set to a value different than 0000, the device is in continuous mode and automatically acquires a set of data (pressure and temperature) at the frequency selected through the ODR[3:0] bits. ILPS28QSW CTRL_REG1 (10h) DS13905 - Rev 1 page 34/52 |
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