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AT25QL321 Fiches technique(PDF) 8 Page - Renesas Technology Corp |
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AT25QL321 Fiches technique(HTML) 8 Page - Renesas Technology Corp |
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8 / 82 page ![]() DS-AT25QL321-131 Rev. D Page 8 Nov 1, 2022 © 2022 Renesas Electronics AT25QL321 Datasheet 2. Pinouts and Pin Descriptions Figure 1 shows the available package types. Figure 1. Package Types During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL. 8-UDFN (Top View) 8-pad USON (Top View) 8-WLCSP (Bottom View) CS SO (IO 1) WP (IO 2, ACC) GND 1 2 3 4 8 7 6 5 VCC HOLD (IO 3) SCK SI (IO 0) SO (IO 1) GND SI (IO 0) VCC HOLD (IO 3) SCK WP (IO 2, ACC) CS 1 2 3 4 8 7 6 5 GND I/O 0 (SI) SCK I/O 1(SO) Vcc I/O 3(HOLD) (I/O 2, ACC) WP CS |
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