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STM32U595AI Fiches technique(PDF) 309 Page - STMicroelectronics

No de pièce STM32U595AI
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, up to 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI
PDF  377 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U595AI Fiches technique(HTML) 309 Page - STMicroelectronics

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DS13633 Rev 1
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STM32U59xxx
Electrical characteristics
343
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 55 to Figure 58 represent asynchronous waveforms and Table 123 to Table 130
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
•
AddressSetupTime (ADDSET) = 0x1
•
AddressHoldTime (ADDHLD) = 0x1
•
ByteLaneSetup (NBLSET) = 0x1
•
DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,
DataSetupTime = 0x5)
•
DataHoldTime (DATAHLD) = 0x1 (0x0 for write operation)
•
BusTurnAroundDuration = 0x0
•
Capacitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period.
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
Data
FMC_NE
FMC_NBL[1:0]
FMC_D[15:0]
tv(BL_NE)
t h(Data_NE)
FMC_NOE
Address
FMC_A[25:0]
tv(A_NE)
FMC_NWE
tsu(Data_NE)
tw(NE)
MS32753V1
w(NOE)
t
tv(NOE_NE)
t h(NE_NOE)
th(Data_NOE)
t h(A_NOE)
t h(BL_NOE)
tsu(Data_NOE)
FMC_NADV (1)
t v(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)



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