82P33741 datasheet(13/59 Pages) RENESAS

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September 15, 2017

82P33741 Datasheet

Figure 4. DPLL Automatic Operating Mode

Notes to Figure 4:

1. Reset.

2. An input clock is selected.

3. The DPLL selected input clock is disqualified AND No qualified input clock is available.

4. The DPLL selected input clock is switched to another one.

5. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).

6. The DPLL selected input clock is disqualified AND No qualified input clock is available.

7. The DPLL selected input clock is unlocked (the DPLL_LOCK bit is ‘0’).

8. The DPLL selected input clock is locked again (the DPLL_LOCK bit is ‘1’).

9. The DPLL selected input clock is switched to another one.

10. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).

11. The DPLL selected input clock is disqualified AND No qualified input clock is available.

12. The DPLL selected input clock is switched to another one.

13. The DPLL selected input clock is disqualified AND No qualified input clock is available.

14. An input clock is selected.

15. The DPLL selected input clock is switched to another one.

The causes of Item 4, 9, 12, 15 - ‘the DPLL selected input clock is

switched to another one’ - are: (The DPLL selected input clock is dis-

qualified AND Another input clock is switched to) OR (In Revertive

switching, a qualified input clock with a higher priority is switched to) OR

(The DPLL selected input clock is switched to another one Forced selec-

tion).

Free-Run m ode

Pre-Locked

m ode

Locked

m ode

Lost-Phase

m ode

Holdover

m ode

Pre-Locked2

m ode

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