OP490 datasheet(4/16 Pages) AD

4 / 16 page

REV. C

OP490

–4–

+IN

–IN

OUTPUT

V+

V–

Figure 1. Simplified Schematic

Parameter

Symbol

Conditions

Limits

Unit

Input Offset Voltage

VOS

0.75

mV max

Input Offset Current

IOS

VCM = 0 V

nA max

Input Bias Current

VCM = 0 V

nA max

Large Signal Voltage Gain

AVO

VS =

±15 V, VO = ±10 V,

RL = 100 k

500

V/mV min

RL = 10 k

250

V/mV min

V+ = 5 V, V– = 0 V

125

V/mV min

1 V < VO < 4 V, RL = 100 k

Input Voltage Range

IVR

V+ = 5 V, V– = 0 V

0/4

V min

VS =

±15 V*

–15/+13.5

V min

Output Voltage Swing

VS =

±15 V

RL = 10 k

W±13.5

V min

RL = 2 k

W±10.5

V min

VOH

V+ = 5 V, V– = 0 V, RL = 2 k

4.0

V min

VOL

V+ = 5 V, V– = 0 V, RL = 10 k

500

mV max

Common-Mode Rejection Ratio

CMRR

V+ = 5 V, V– = 0 V, 0 V < VCM < 4 V

dB min

VS =

±15 V, –15 V < VCM < +13.5 V

dB min

Power Supply Rejection Ratio

PSRR

mV/V max

Supply Current (All Amplifiers)

ISY

VS =

±15 V, No Load

mA max

NOTE

*Guaranteed by CMRR test.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

WAFER TEST LIMITS (@ V

S =

1.5 V to

15 V, TA = 25 C, unless otherwise noted)

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