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HC705RC17GRS/D Fiches technique(PDF) 95 Page - NXP Semiconductors |
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HC705RC17GRS/D Fiches technique(HTML) 95 Page - NXP Semiconductors |
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95 / 126 page ![]() EPROM Bootloader MC68HC705RC17 — Rev. 3.0 General Release Specification EPROM IRQ — IRQ sensitivity 1 = This bit selects the edge- and level-sensitive IRQ. 0 = IRQ is edge-only sensitive. STOP — STOP Enable 1 = This bit enables the STOP instruction. 0 = A STOP instruction is equivalent to a WAIT instruction. COP — COP Enable 1 = This bit enables the COP watchdog timer. 0 = The COP is disabled. NOTE: The port B keyscan interrupt sensitivity will match that of the IRQ sensitivity. (See 4.7 External Interrupt (IRQ/Port B Keyscan) for more information.) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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