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AS7C31026-15JC Fiches technique(PDF) 4 Page - Alliance Semiconductor Corporation |
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AS7C31026-15JC Fiches technique(HTML) 4 Page - Alliance Semiconductor Corporation |
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4 / 10 page ![]() ® AS7C1026 AS7C31026 3/23/01; v.1.0 Alliance Semiconductor P. 4 of 10 Read cycle (over the operating range)3,9 Shaded areas indicate preliminary information. Key to switching waveforms Read waveform 1 (address controlled)3,6,7,9 Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 Parameter Symbol -12 -15 -20 Unit Notes Min Max Min Max Min Max Read cycle time tRC 12 – 15 – 20 – ns Address access time tAA –12–15 – 20 ns 3 Chip enable (CE) access time tACE –12–15 – 20 ns 3 Output enable (OE) access time tOE – 6 –7 –8 ns Output hold from address change tOH 4– 4– 4– ns 5 CE Low to output in low Z tCLZ 0– 0– 0– ns 4, 5 CE High to output in high Z tCHZ – 6 –6 –8 ns 4, 5 OE Low to output in low Z tOLZ 0– 0– 0– ns 4, 5 Byte select access time tBA – 6 –7 –8 ns Byte select Low to low Z tBLZ 0– 0– 0– ns 4,5 Byte select High to high Z tBHZ – 6 –6 –8 ns 4,5 OE High to output in high Z tOHZ – 6 –6 –8 ns 4, 5 Power up time tPU 0– 0– 0– ns 4, 5 Power down time tPD –12–15 – 20 ns 4, 5 Undefined output/don’t care Falling input Rising input tOH tAA tRC tOH DataOUT Address Data valid Previous data valid Data valid tRC tAA tBLZ tBA tOE tOLZ tOH tOHZ tHZ tBHZ tACE tLZ Address OE CE LB, UB DataIN |
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