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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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74HC190D Fiches technique(PDF) 13 Page - NXP Semiconductors |
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74HC190D Fiches technique(HTML) 13 Page - NXP Semiconductors |
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13 / 13 page  December 1990 13 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the clock (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. |
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