6

Application information

6.1

VBIAS pin voltage requirements

The bias input is the supply of the internal driving and control circuitry. In order to ensure proper biasing of the N-

channel power element, the bias pin must have a minimum voltage of 2.4 V and 1.6 V (typically) higher than the

output. If VIN supply voltage meets these requirements then the bias pin can be tied to VIN.

6.2

Output discharge function

The LD56050 integrates a MOSFET connected between VOUT and GND. This transistor is activated when the EN

pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is

disabled by the user.

6.3

Short circuit and current limitation

The LD56050 is protected against short-circuit on the output. The load current is limited to the maximum value of

ILIM when VOUT is equal to 90% of its nominal value. If the VOUT decreases even more due to a lower output load

resistance then the foldback circuit starts operating limiting the current to ISC when VOUT = 0.

6.4

Thermal protection

Thermal protection acts when the junction temperature reaches 160 °C typical. At this point the output of the IC

shuts down. As soon as the junction temperature falls below the thermal hysteresis value the device starts

working again.

In order to calculate the maximum power that the device can dissipate, keeping the junction temperature below

the maximum operating value, the following formula is used:

PDMAX = (85 - TAMB) / RthJA

6.5

Input and output capacitors

The LD56050 requires external capacitors to assure the regulator control loop stability.

Any good quality ceramic capacitor can be used but, the X5R and the X7R are suggested since they guarantee a

very stable combination of capacitance and ESR across the temperature range.

Locating the input/output capacitors as close as possible to the relative pins is recommended. The LD56050

requires a VIN capacitor with a minimum value of 1 μF and a VBIAS capacitor of 100 nF minimum. These

capacitors must be located as close as possible to the input pins of the device and returned to a clean analog

ground.

The control loop is designed to be stable with any good quality output ceramic capacitor (such as X5R/X7R types)

with a minimum value of 1.0 μF and equivalent series resistance in the [3 – 300 mΩ] range. It is important to

highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full

operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR

variations must be taken into account in the design phase to ensure the device works in the expected stability

region.

LD56050

Application information

DS12441 - Rev 2

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