74HC160DB datasheet(2/9 Pages) PHILIPS

2 / 9 page

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous BCD decade

counter; asynchronous reset

74HC/HCT160

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive-edge triggered clock

• Asynchronous reset

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT160 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT160 are synchronous presettable decade

counters which feature an internal look-ahead carry and

can be used for high-speed counting.

Synchronous operation is provided by having all flip-flops

clocked simultaneously on the positive-going edge of the

clock (CP).

The outputs (Q0 to Q3) of the counters may be preset to a

HIGH or LOW level. A LOW level at the parallel enable

input (PE) disables the counting action and causes the

data at the data inputs (D0 to D3) to be loaded into the

counter on the positive-going edge of the clock (providing

that the set-up and hold time requirements for PE are met).

Preset takes place regardless of the levels at count enable

inputs (CEP and CET).

A LOW level at the master reset input (MR) sets all four

outputs of the flip-flops (Q0 to Q3) to LOW level regardless

of the levels at CP, PE, CET and CEP inputs (thus

providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the

counters. Both count enable inputs (CEP and CET) must

be HIGH to count. The CET input is fed forward to enable

the terminal count output (TC). The TC output thus

enabled will produce a HIGH output pulse of a duration

approximately equal to a HIGH level output of Q0. This

pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters

is determined by the CP to TC propagation delay and CEP

to CP set-up time, according to the following formula:

fmax =

P max

()

CP to TC

() +t

SU (CEP to CP)

---------------------------------------------------------------------------------------------------------

QUICK REFERENCE DATA

GND = 0 V; Tamb=25 °C; tr =tf = 6 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL

propagation delay

CP to Qn

CP to TC

MR to Qn

MR to TC

CET to TC

CL =15pF;

VCC =5V

tPLH

propagation delay

CP to Qn

CP to TC

CET to TC

fmax

maximum clock

frequency

MHz

input capacitance

3.5

CPD

power dissipation

capacitance per

package

notes 1 and 2

Notes

1. CPD is used to determine the

dynamic power dissipation

(PD in µW):

PD =CPD × VCC2 × fi +

∑ (CL × VCC2 × fo)

where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of

outputs

CL = output load capacitance in

VCC = supply voltage in V

2. For HC the condition is

VI = GND to VCC

For HCT the condition is

VI = GND to VCC − 1.5 V

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