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UPSD325X Fiches technique(PDF) 165 Page - STMicroelectronics |
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UPSD325X Fiches technique(HTML) 165 Page - STMicroelectronics |
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165 / 176 page ![]() 165/176 µPSD325X DEVICES Figure 84. Peripheral I/O WRITE Timing Table 133. Port A Peripheral Data Mode WRITE Timing (5V Devices) Note: 1. Data stable on Port 0 pins to data on Port A. Table 134. Port A Peripheral Data Mode WRITE Timing (3V Devices) Note: 1. Data stable on Port 0 pins to data on Port A. Symbol Parameter Conditions Min Max Unit tWLQV–PA WR to Data Propagation Delay 25 ns tDVQV–PA Data to Port A Data Propagation Delay (Note 1) 22 ns tWHQZ–PA WR Invalid to Port A Tri-state 20 ns Symbol Parameter Conditions Min Max Unit tWLQV–PA WR to Data Propagation Delay 42 ns tDVQV–PA Data to Port A Data Propagation Delay (Note 1) 38 ns tWHQZ–PA WR Invalid to Port A Tri-state 33 ns tDVQV (PA) tWLQV (PA) tWHQZ (PA) ADDRESS DATA OUT A / D BUS WR PORT A DATA OUT ALE AI06611 |
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