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UPSD325X Fiches technique(PDF) 160 Page - STMicroelectronics

No de pièce UPSD325X
Description  Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
PDF  176 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD325X Fiches technique(HTML) 160 Page - STMicroelectronics

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Figure 80. Asynchronous RESET / Preset
Figure 81. Asynchronous Clock Mode Timing (product term clock)
Table 125. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
Rate
Unit
fMAXA
Maximum Frequency
External Feedback
1/(tSA+tCOA)
38.4
MHz
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
62.5
MHz
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
71.4
MHz
tSA
Input Setup Time
7
+ 2
+ 10
ns
tHA
Input Hold Time
8
ns
tCHA
Clock Input High Time
9
+ 10
ns
tCLA
Clock Input Low Time
9
+ 10
ns
tCOA
Clock to Output Delay
21
+ 10
– 2
ns
tARDA
CPLD Array Delay
Any macrocell
11
+ 2
ns
tMINA
Minimum Clock Period
1/fCNTA
16
ns
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCHA
tCLA
tCOA
tHA
tSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859



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