AOZ9510QI datasheet(10/13 Pages) AOSMD

10 / 13 page

Rev. 1.3 September 2022

www.aosmd.com

Page 10 of 13

AOZ9510QI

Layout Considerations

Several layout tips are listed below for the best electric

and thermal performance.

1. The VIN pins and pad are connected to internal high

side switch drain. They are also low resistance

thermal conduction path. Connected a large copper

plane to VIN pins to help thermal dissipation.

2. Input capacitors should be connected to the VIN pins

and the PGND pins as close as possible to reduce

the switching spikes.

3. The VOUT pins and pad are connected to internal

low side switch drain. They are low resistance

thermal conduction path and most noisy switching

node. Connected a large copper plane to VOUT pins

to help thermal dissipation.

4. Decoupling capacitor CVCC should be connected to

VCC and AGND as close as possible.

5. Bootstrap capacitor CB should be connected to VB

and VOUT as close as possible.

6. A ground plane is preferred; PGND and AGND must

be connected to the ground plane through vias.

7. Keep sensitive signal traces such as feedback trace

and digital signals far away from the VOUT pins.

Figure 13. Layout Placement

VIN

VOUT

DVS2

DVS1

HIN

LIN

VTP

PGND

AOZ9510QI Fiches technique(PDF) 10 Page - Alpha & Omega Semiconductors