MCP6L71RT-ESLASHMS datasheet(14/40 Pages) MICROCHIP

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MCP6L71/1R/2/4

DS20002145B-page 14

 2009-2019 Microchip Technology Inc.

4.4

Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good, high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with nearby analog parts.

4.5

Unused Amplifiers

An unused op amp in a quad package (MCP6L74)

should be configured as shown in Figure 4-3. These

circuits prevent the output from toggling and causing

crosstalk. In Circuit A, R1 and R2 produce a voltage

within its output voltage range (VOH, VOL). The op amp

buffers this voltage, which can be used elsewhere in

the circuit. Circuit B uses the minimum number of

components and operates as a comparator.

FIGURE 4-3:

Unused Op Amps.

4.6

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

. A 5V difference would

cause 5 pA of current to flow. This is greater than the

MCP6L71/1R/2/4 family’s bias current at +25°C (1 pA,

typical).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

Figure 4-4 shows an example of this type of layout.

FIGURE 4-4:

Example Guard Ring Layout.

For Inverting Gain and Transimpedance Amplifiers

(convert current to voltage, such as photo

detectors):

a) Connect the guard ring to the noninverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the

op amp (e.g., VDD/2 or ground).

b) Connect the inverting pin (VIN-) to the input

with a wire that does not touch the PCB

surface.

Noninverting Gain and Unity Gain Buffer:

a) Connect the guard ring to the inverting input

pin (VIN-). This biases the guard ring to the

Common-mode input voltage.

b) Connect the noninverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

4.7

Application Circuits

4.7.1

INVERTING INTEGRATOR

An inverting integrator is shown in Figure 4-5. The

circuit provides an output voltage that is proportional to

the negative time integral of the input. The additional

resistor R2 limits DC gain and controls output clipping.

To minimize the integrator’s error for slow signals, the

value of R2 should be much larger than the value of R1.

FIGURE 4-5:

Inverting Integrator.

¼MCP6L74 (A)

VDD

¼ MCP6L74 (B)

VDD

VREF

VDD

R1 R2

------------------



–

Guard Ring

VIN-VIN+

VIN

VOUT

MCP6L71

R2 R1

VOUT

R1C1

------------- VIN t



–

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