DRV8317H datasheet(26/69 Pages) TI

26 / 69 page

8.3.9.3 Open Drain Pin

Figure 8-16 shows the structure of the open-drain output pin nFAULT. The open-drain output requires an external

pullup resistor to a logic voltage supply to function properly.

AVDD

Inactive

OUTPUT

No Fault

STATE

Pulled-Up

STATUS

Fault

Pulled-Down

Active

RPU

ESD

Figure 8-16. Open Drain Output Pin Structure

8.3.9.4 Push Pull Pin

Figure 8-17 shows the structure of the push-pull pin SDO.

AVDD

VOH

STATE

Pulled-Up

STATUS

VOL

Pulled-Down

Logic High

OUTPUT

Logic Low

ESD

Hi-Z

Open

Hi-Z

Figure 8-17. Push-Pull Output Pin Structure

8.3.9.5 Four Level Input Pin

Figure 8-18 shows the structure of the four level input pins GAIN, MODE and SLEW on hardware interface

devices. The input can be set by tying the pin to AGND or AVDD, leaving the pin unconnected, or connecting an

external resistor from the pin to ground.

Setting-1

CONTROL

Setting-2

Setting-3

Setting-4

–

VL1

STATE

Tied to AGND

RESISTANCE

VL2

47 k

±5%

to AGND

VL3

Hi-Z

VL4

Tied to AVDD

AVDD

RPU

RPD

AVDD

Figure 8-18. Four Level Input Pin Structure

DRV8317

SLVSGT3 – DECEMBER 2022

www.ti.com

Submit Document Feedback

Product Folder Links: DRV8317

DRV8317H Fiches technique(PDF) 26 Page - Texas Instruments

DRV8317H Fiches technique(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Fiches technique Télécharger

Lien URL